Traditional CMOS (complementary metal oxide semiconductor) techniques include process flows for constructing planar FET devices. With planar FETs, increased transistor density can be achieved by decreasing the pitch between transistor gate elements. However, with planar FET devices, the ability to decrease gate pitch is limited by the required gate length and spacer thickness. In recent years, there has been significant research and development with regard to vertical FET devices, which decouple the gate length from the gate pitch requirement and enable scaling of transistor density. In general, vertical FET devices are designed to have gate structures that are formed on multiple sides of a vertical channel structure (e.g., a vertical semiconductor fin or vertical nanowire). In addition, vertical FET devices employ doped source and drain regions, wherein a doped source region for a vertical FET can be formed on top of a vertical semiconductor fin, and wherein a doped drain region can be formed underneath the vertical semiconductor fin. With vertical FET devices, scaling is determined by how close vertical conductive contacts to the source and drain regions can be placed.
In semiconductor devices where different pattern densities of device structures are formed on a semiconductor substrate, the ability to fabricate device structures with uniform structural profiles within the same device region or adjacent device regions is problematic and challenging because of the micro-loading effects of conventional etch and planarizing processes. For example, with vertical FET devices, a gate length of a metal gate is defined by a timed etching of a layer of conductive gate material, typically performed by a reactive ion etch (RIE). Due to the micro-loading effects of the RIE process, there can be a relatively large variation in the gate length of vertical FET devices between dense vertical FET regions and isolated vertical FET regions. Indeed, the metal gate recess level in a given region is dependent, for example, on the pattern density of vertical semiconductor fins (e.g., pitch) within the given region, where the conductive gate layer may be recessed deeper in regions of the semiconductor substrate having relaxed-pitch vertical semiconductor fin patterns as compared to regions of the semiconductor substrate having tight-pitch vertical semiconductor fin patterns. Even within the same device region, gate length variation can occur between vertical FET devices formed within a center region of a given device region and vertical FET devices formed at the edges of the given device region.
Another issue with conventional vertical FET device fabrication is the initial variation in thickness of a planarized layer of conductive gate material (prior to the gate recess), which results from dishing effects that can result from chemical mechanical polishing (CMP). The micro-loading effects of conventional etch and planarizing processes during vertical FET device fabrication can result in undesired variation in device dimensions, which leads to undesired variation in device performance.